STV9410 datasheet(13/25 Pages) STMICROELECTRONICS

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TIMING DIAGRAM

DESIGNATION

COMMENTS

PIXEL CLOCK

Y OUTPUT

START

”HORT” MSB REG

”HORT” LSB REG

”HSYN” LSB REG

”HSYN” MSB REG

HSYN PULSE

0 Start

Margin

Active Area (320 pixels)

START

Margin

End of line

8pxlck Fixed

= (MG +1) x 8 x pxlck

= (L +1) x 8 x pxlck

= (SD + 1) x 2 x pxlck

= (SU + 1) x 2 x pxlck

0 = origin

DAC output

Crystal = 8MHz

pxlck = 125ns

Figure 8 : Horizontal Synchronization Timing

Video Validation and Port Register (PORT)

Internal address : 2FF7-2FF6 h

RESET value :00-00 h

(@ = RESET default configuration)

2FF7

VOE

----

000

2FF6

000

VOE

Video Output Enable

1 enable synchro & video outputs

0 disable synchro & video outputs @

(@ Output Y, CSYNC,VSYNC, R, G, B, I, POR,

and DF are grounded, Input SYNC IN is high

impedance)

Timer Enable

1 POR provides a square wave signal with a

period of 16 x N(7:0) x pxlck

0 POR output is PV bit @

Port Value

POR output value if TE=0 (@=0)

N(7:0)

Square wave period on POR if TE=1 (@=0)

BEWARE

The programmation of VERT, HORI, HSYN regis-

ters must be consistent. To get a proper work of the

controller, the following conditions must, in any

mode (CRT or LCD), be fulfiled :

-SU

≠ SD

+ 1

< L and

+ 1

- 2(MG + 1) + 40

≤ L

Line period is :

-PL = [L(5:0) + 1] x 8 pxlck

- In LCD, MG(2:0) can be 0, then minimum Line

Period is PL (min.) = 43 x 8 pxlck

Frame period is :

-PF = [F(8:0) + 2] x PL

- In LCD, using a 240 lines matrix, F(8:0) = 238,

then minimum frame is :

PF (min.) = 240 x 43 x 8 pxclk

Pixel period is :

- Pxclk =

PFrame

(8:0)+ 2 ][ L(5:0)+ 1] x 8

- I n LC D, u si ng a 240 li ne s m atr i x, an d

MG(2:0) = 0, Pxclk =

PFrame

240 x 43 x 8

Interlaced mode conditions :

+ 1

and

+ 1

and

+ 1

> (MG + 1) + 42

STV9410

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