STV9410 datasheet(5/25 Pages) STMICROELECTRONICS

5 / 25 page

TIMINGS

(VDD =5V

±5%, VSS =0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz,

VIL = 0.8V, VIH =2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified)

Symbol

Parameter

Min

Typ

Max

Unit

SERIAL INTERFACE NCS, SCK, SDA (Figure 1)

Tcsl

NCS low to SCK falling edge

Tsch

SCK pulse width high

Tscl

SCK pulse width low

fSCK

Serial Clock Frequency

MHz

Tsds

Set up time of SDA on SCK rising edge

Tsdh

Hold time of SDA after SCK rising edge

Tsdv

Access time in read mode

Tsdx

Hold data in read mode

Tsdz

Serial interface disable time

Tread

Delay before Valid Data

µs

OSCILLATOR INPUT (XTI) (Figure 1)

Twh

Clock high level

Twl

Clock low level

Fclk

Clock frequency

MHz

RESET (VREF)

Tres

Reset Low level pulse

µs

OUTPUT SIGNALS SDA, CSYNC,VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2)

Tph,Tpl

Propagation time

CL =30 pF

CL = 100 pF

100

Tskew

Skew between R, G, B, I signals

(VDD =5V

±5%, VSS =0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz,

VOL = 0.2VDD,VOH = 0.8VDD,CL = 100pF, unless otherwise specified)

LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3)

tCYC

CKD Shift Clock Period

4 x Pxtal

tCH

CKD Clock High

150

tCL

CKD Clock Low

150

tWLD

Load Pulse Width

150

tSU

Data Set-up Time

150

tDH

Data Hold Time

150

tDF

DF Delay from Load

100

tSUF

Frame Set-up before Load

150

STV9410

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