STV9432TAP

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Table 2

CLUT Block Selection

12.2 - OSD CONTROL REGISTERS

Line Duration (reset value: 20H)

Top Margin (reset value: 30H)

Note: The top margin is displayed before the first strip of descriptor list. It can be black if FBK of DISPLAY CONTROL

register is set or transparent if FBK is clear.

Horizontal Delay (reset value: 20H)

CLU3

CLU[2:0]

Code Name

Command Code

(hex)

Ram @(hex)

Reset Value (hex)

0

Col 0

00

@4020

07

1

Col 1

01

@4021

16

0

2

Col 2

02

@4022

25

3

Col 3

03

@4023

34

4

Col 4

04

@4024

43

5

Col 5

05

@4025

52

6

Col 6

06

@4026

61

7

Col 7

07

@4027

70

0

Col 0

00

@4028

70

1

Col 1

01

@4029

61

2

Col 2

02

@402A

52

1

3

Col 3

03

@402B

43

4

Col 4

04

@402C

34

5

Col 5

05

@402D

25

6

Col 6

06

@402E

16

7

Col 7

07

@402F

07

4030

VSP

HSP

LD6

LD5

LD4

LD3

LD2

LD1

VSP

:

V-SYNC active edge selection

= 0, falling egde,

= 1, rising edge.

HSP

:

HFLY active edge selection

= 0, rising egde,

= 1, falling edge.

LD[6:1]

:

LINE DURATION

LD0 = 0

LD1 = 2 periods of character

One character period is 12 pixels long.

4031

M9

M8

M7

M6

M5

M4

M3

M2

M[9:2]

:

TOP MARGIN height from the VSYNC reference edge.

M0 = 0, M1 = 0

M2 = 4 scan lines

4032

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

DD[7:0]

:

ter strips.

Unit = 6 pixel periods. Minimum value is 08H. First pixel position = [DD[7:0] - 6] x 6 + 54 with

DD[7:0] = 0,2,4,6 delay is 54 pixel and with DD[7:0] = 1,3,5 delay is 60 pixel