STV9432TAP

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6 - TIMINGS

Notes:

- These parameters are not tested on each unit. They are measured during our internal qualification procedure which

includes characterization on batches coming from corners of our processes and also temperature characterization.

- The ADC measurements are dependant on the noise. The test is done by correlation in order to screen out marginal

devices.

Figure 1.

Symbol

Parameter

Min.

Typ.

Max.

Unit

OSCILLATOR

Clock Frequency

8

MHz

Maximum Pixel Frequency

100

MHz

Rise Time (see Note 1)

5ns

Fall Time (see Note 1)

5ns

Skew between R, G, B, FBLK

5ns

SCL Clock Frequency

0

400

kHz

Time the bus must be free between 2 access

500

ns

Hold Time for Start Condition

500

ns

Set up Time for Stop Condition

500

ns

The Low Period of Clock

400

ns

The High Period of Clock

400

ns

Hold Time Data

0ns

Set up Time Data

500

ns

Fall Time of SDA

20

ns

Rise Time of both SCL and SDA

Depend on the pull-up resistor and the

load capacitance

ANALYZER (HS, HFLY, AV)

Low Pulse Width (see Note 3)

2

4091

High Pulse Width

2

4091

Hs

Hs Frequency

Hfly

ANALYZER (VS)

Low Pulse Width

2

4091

Lines

High Pulse Width

2

4091

Lines

SDA

SCL

STOP START

DATA

t

BUF

t

HDAT

STOP