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M66596FP 数据表(PDF) 62 Page - Renesas Technology Corp |
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M66596FP 数据表(HTML) 62 Page - Renesas Technology Corp |
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62 / 131 page ![]() M66596FP/WG rev .1.00 2006.3.14 page 62 of 127 Figure 3.12 shows a diagram relating to controller interrupts. INT_N Edge / Level Generation Circuit INTENB0 INTSTS0 DVST DVSE VBINT VBSE RESM RSME SOFR SOFE CTRT CTRE BEMP BEMPE NRDY NRDYE BRDY BRDYE USB reset detected Set_Address detected Set_Configuration detected Suspended state detected URST SADR SCFG SUSP End Control Transfer Data Stage Data Stage Error WDST RDST CMPL SERR Setup Receive Control Write Control Read Control Transfer Control Transfer b7 b1 b0 b0 b1 b7 . . . . . … b7 b1 b0 b0 b1 b7 . . . . . … b7 b1 b0 b0 b1 b7 . . . . . … BEMPENB NRDYENB BRDYENB BEMPSTS NRDYSTS BRDYSTS INTENB0 BCHE BCHGE DTCH DTCHE SIGN SIGNE SACK SACKE INTENB1 INTSTS1 Figure 3.12 Items relating to interrupts |
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