M66596FP datasheet(2/131 Pages) RENESAS

2 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 2 of 127

1.2.5

Bus interfaces

•

The user can select either a 1.8 V or 3.3 V bus interface power supply

•

16-bit CPU bus interface

16-bit separate bus and 16-bit multiplex bus supported

8 and 16-bit DMA interface (slave function) supported

•

8-bit split bus (dedicated external DMA interface) supported

•

Built-in two DMA interface channels

•

DMA transfer enables high-speed access of 40 MB/sec.

1.2.6

Pipe configuration

•

Built-in 5 KB buffer memory for USB communication

•

Up to 8 pipes(endpoints) can be selected (including the default control pipe for endpoint 0)

•

Programmable pipe configuration

•

End point numbers can be assigned to pipe 1-7.

•

Transfer conditions that can be set for each pipes

Pipe 0: Control transfer, continuous transfer mode, 256-byte fixed single buffer

Pipe 1 and 2: Bulk transfer or isochronous transfer, continuous transfer mode, programmable buffer size

(up to 2 KB; double buffer can be selected)

Pipe 3 to 5: Bulk transfer, continuous transfer mode, programmable buffer size

(up to 2 KB; double buffer can be selected)

Pipe 6 and 7: Interrupt transfer, 64-byte fixed single buffer

1.2.7

Feature in host mode

•

Capable of USB Hi-Speed transfer to one peripheral device.

•

Automatic schedule to send SOF and transaction.

•

Automatic schedule interval of isochronous trenasfer and interrupt transfer.

1.2.8

Feature in peripheral mode

•

Control transfer stage control function

•

Device state control function

•

Auto response function for SET_ADDRESS request

•

NAK response assignment function (NRDY)

1.2.9

Other functions

•

Automatic recognition of Hi-Speed operation or Full-Speed operation based on automatic response to the reset

handshake

•

Byte endian swap function when using 16-bit data transfers

•

Transfer termination function when using transaction count function.

•

DMA transfer termination function using external trigger (DEND pin)

•

SOF interpolation function

•

SOF pulse output function

•

Three types of input clocks can built into the PLL and are available for selection

Input clocks of 48 MHz / 24 MHz / 12 MHz can be selected

•

Zero-Length packet addition function (DEZPM) when ending DMA transfers using the DEND pin

•

BRDY interrupt event notification timing change function (BFRE)

•

Function that automatically clears the buffer memory after the data for the pipe specified at the DxFIFO port

has been read (DCLRM)

•

Function to automatically supply a clock from the low-power sleep state (ATCKM)

•

NAK setting function for response PID generated by end of transfer (SHTNAK)

1.2.10 Applications

PDA, DVD recorder, Set top box, Digital TV, Printer , USB audio devce, Digital video camera, Digital still camera,

external storage device, and Hi-Speed USB devices

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