R8C2K datasheet(91/471 Pages) RENESAS

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R8C/2K Group, R8C/2L Group

10. Clock Generation Circuit

Rev.1.10

Dec 21, 2007

Page 74 of 450

REJ09B0406-0110

Figure 10.3

CM0 Register

System Clock Control Register 0

(1)

Symbol

Address

After Reset

CM0

0006h

01101000b

Bit Symbol

Bit Name

Function

NOTES:

b7 b6 b5 b4 b3 b2 b1 b0

00 1

0 0

—

(b1-b0)

Reserved bits

Set to 0.

CM02

WAIT peripheral function clock

stop bit

0 : Peripheral function clock does not stop

in w ait mode

1 : Peripheral function clock stops in w ait

mode

—

(b3)

Reserved bit

Set to 1.

—

(b4)

Reserved bit

Set to 0.

CM05

XIN clock (XIN-XOUT)

stop bit(2, 3)

0 : XIN clock oscillates

1 : XIN clock stops(4)

CM06

System clock division select bit

0(5)

0 : CM16, CM17 enabled

1 : Divide-by-8 mode

—

(b7)

Reserved bit

Set to 0.

Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.

During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.

When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the

CM1 register is set to 0 (P4_6, P4_7).

The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode or low -speed on-chip oscillator mode

is selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the

follow ing order:

(a) Set bits OCD1 to OCD0 in the OCD register to 00b.

(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).

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