R8C2K datasheet(93/471 Pages) RENESAS

93 / 471 page

R8C/2K Group, R8C/2L Group

10. Clock Generation Circuit

Rev.1.10

Dec 21, 2007

Page 76 of 450

REJ09B0406-0110

Figure 10.5

OCD Register

Oscillation Stop Detection Register

(1)

Symbol

Address

After Reset

OCD

000Ch

00000100b

Bit Symbol

Bit Name

Function

NOTES:

b7 b6 b5 b4 b3 b2 b1 b0

0000

OCD1

OCD0

Oscillation stop detection enable

bit(7)

Oscillation stop detection

interrupt enable bit

0 : Oscillation stop detection function

disabled(2)

1 : Oscillation stop detection function

enabled

0 : Disabled(2)

1 : Enabled

OCD2

System clock select bit(4)

0 : Selects XIN clock(7)

1 : Selects on-chip oscillator clock(3)

OCD3

Clock monitor bit(5, 6)

0 : XIN clock oscillates

1 : XIN clock stops

—

(b7-b4)

Reserved bits

Set to 0.

The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.

The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock

selected).

Refer to Figure 10.14 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN

Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.

Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.

The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected

w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains

unchanged even w hen set to 0 (XIN clock selected).

The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).

Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip

oscillator mode (XIN clock stops).

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