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R8C2K 数据表(PDF) 119 Page - Renesas Technology Corp |
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R8C2K 数据表(HTML) 119 Page - Renesas Technology Corp |
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119 / 471 page  R8C/2K Group, R8C/2L Group 12. Interrupts Rev.1.10 Dec 21, 2007 Page 102 of 450 REJ09B0406-0110 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, TRD0IC, and TRD1IC and Figure 12.5 shows the INTiIC Register. Figure 12.3 Interrupt Control Register Interrupt Control Register (2) Address After Reset 004Bh XXXXX000b 004Ch XXXXX000b 004Dh XXXXX000b 004Eh XXXXX000b 0051h XXXXX000b 0052h XXXXX000b 0056h XXXXX000b 0058h XXXXX000b Bit Symbol Function RW NOTES: 1. 2. Symbol ADIC Bit Name Interrupt priority level select bits TRBIC S2TIC S2RIC TRAIC KUPIC S0TIC S0RIC Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents. b7 b6 b5 b4 b3 b2 b1 b0 RW b2 b1 b0 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILVL1 RW ILVL2 RW ILVL0 Only 0 can be w ritten to the IR bit. Do not w rite 1. IR 0 : Requests no interrupt 1 : Requests interrupt RW(1) — (b7-b4) — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Interrupt request bit |
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