R8C2K datasheet(124/471 Pages) RENESAS

124 / 471 page

R8C/2K Group, R8C/2L Group

12. Interrupts

Rev.1.10

Dec 21, 2007

Page 107 of 450

REJ09B0406-0110

12.1.6.5

Interrupt Response Time

Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt

request generation and the execution of the first instruction in the interrupt routine. The interrupt response time

includes the period between interrupt request generation and the completion of execution of the instruction

(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in

Figure 12.7).

Figure 12.7

Interrupt Response Time

12.1.6.6

IPL Change when Interrupt Request is Acknowledged

When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the

acknowledged interrupt is set in the IPL.

When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the

IPL.

Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.

Table 12.5

IPL Value When Software or Special Interrupt Is Acknowledged

Interrupt Source

Value Set in IPL

Watchdog timer, oscillation stop detection, voltage monitor 1,

voltage monitor 2, Address break

Software, address match, single-step

Not changed

Interrupt request is generated. Interrupt request is acknowledged.

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

(a)

20 cycles (b)

Interrupt response time

(a) Period between interrupt request generation and the completion of execution of an

instruction. The length of time varies depending on the instruction being executed. The

DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a

(b) 21 cycles for address match and single-step interrupts.

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