HD6417618A datasheet(38/646 Pages) RENESAS

部件名	HD6417618A

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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38 / 646 page

Section 1 Overview

Rev. 6.00 Jun. 12, 2007 Page 6 of 610

REJ09B0131-0600

1.2

Block Diagram

Figure 1.1 is a block diagram of this LSI.

SuperH

CPU core

User break

controller

(UBC)

Cache

access

controller

(CCN)

U memory

4 kbytes

Cache

memory

4 kbytes

(SH7618)

16 kbytes

(SH7618A)

Bus state

controller

(BSC)

Peripheral

bus

controller

Ethernet

controller

direct memory

access

controller

(E-DMAC)

CPU bus (I clock)

Internal bus (B clock)

External bus

Notes:

Host

interface

(HIF)

User

debugging

interface

(H-UDI)

Interrupt

controller

(INTC)

Power-

down

mode

control

Watchdog

timer

(WDT)

Clock pulse

generator

(CPG)

Serial

communication

interface

with FIFO

(SCIF)*1

Transmit FIFO

(256 bytes (SH7618))

Ethernet controller

(EtherC)

Receive FIFO

(512 bytes (SH7618A))

Peripheral bus (P clock)

I/O port,

Pin function

controller

(PFC)

Compare

match timer

(CMT)*2

1-kbyte

SRAM

1. SCIF includes three channels.

2. CMT includes two channels.

Figure 1.1 Block Diagram

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