HD6417618A datasheet(107/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 75 of 610

REJ09B0131-0600

5.5.3

Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is called “instruction placed

in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot

exception handling starts after the undefined code is decoded. Illegal slot exception handling also

starts when an instruction that changes the program counter (PC) value is placed in a delay slot

and the instruction is decoded. The CPU handles an illegal slot instruction as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the

delayed branch instruction immediately before the undefined code or the instruction that

rewrites the PC.

3. The start address of the exception handling routine is fetched from the exception handling

vector table that corresponds to the exception that occurred. Program execution branches to

that address and the program starts. This branch is not a delayed branch.

5.5.4

General Illegal Instructions

When an undefined code placed anywhere other than immediately after a delayed branch

instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts.

The CPU handles the general illegal instructions in the same procedures as in the illegal slot

instructions. Unlike processing of illegal slot instructions, however, the program counter value that

is stacked is the start address of the undefined code.

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