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HD6417618A 数据表(PDF) 114 Page - Renesas Technology Corp |
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HD6417618A 数据表(HTML) 114 Page - Renesas Technology Corp |
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114 / 646 page ![]() Section 6 Interrupt Controller (INTC) Rev. 6.00 Jun. 12, 2007 Page 82 of 610 REJ09B0131-0600 NMI IRQ0 IRQ7 UBC H-UDI WDT E-DMAC CMT0 CMT1 SCIF0 SCIF1 SCIF2 HIF (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Input control Com- parator Interrupt request SR CPU I3 I2 I1 I0 Bus interface IPRA to IPRE ICR0 IRQSR IRQCR Module bus INTC HIF: Host interface ICR0: Interrupt control register 0 IRQCR: IRQ control register IRQSR: IRQ status register IPRA to IPRE: Interrupt priority registers A to E SR: Status register IPR DTER DTC [Legend] UBC: User break controller H-UDI: User debugging interface WDT: Watchdog timer E-DMAC: DMAC for Ethernet controller CMT: Compare match timer SCIF: Serial communications interface with FIFO Priority determination . . . . . . Figure 6.1 INTC Block Diagram |
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