HD6417618A datasheet(179/646 Pages) RENESAS

部件名	HD6417618A

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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179 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 147 of 610

REJ09B0131-0600

When buffers are placed on the data bus, the

RD signal should be used to control the buffers. The

RD/

WR signal indicates the same state as a read cycle (driven high) when no access has been

carried out. Therefore, care must be taken when controlling the buffers with the RD/

WR signal, to

avoid data conflict.

Figures 7.4 and 7.5 show the basic timings of normal space consecutive access. If the WM bit in

CSnWCR is cleared to 0, a Tnop cycle is inserted to check the external wait (figure 7.4). If the

WM bit in CSnWCR is set to 1, an external wait request is ignored and no Tnop cycle is inserted

(figure 7.5).

CKIO

A25 to A0

RD/

D15 to D0

WEn(BEn)

D15 to D0

WAIT

CSn

Tnop

Read

Write

Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits,

Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0)

HD6417618A 数据表(PDF) 179 Page - Renesas Technology Corp