HD6417618A datasheet(243/646 Pages) RENESAS

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Section 9 Watchdog Timer (WDT)

Rev. 6.00 Jun. 12, 2007 Page 211 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select the clock to be used for the

WTCNT count from the eight types obtainable by

dividing the peripheral clock (P

φ). The overflow

period that is shown inside the parenthesis in the

table is the value when the peripheral clock (P

φ) is

25 MHz.

000: P

φ (10 µs)

001: P

φ/4 (41 µs)

010: P

φ/16 (164 µs)

011: P

φ/32 (328 µs)

100: P

φ/64 (655 µs)

101: P

φ/256 (2.62 ms)

110: P

φ/1024 (10.49 ms)

111: P

φ/4096 (41.94 ms)

Note:

If bits CKS2 to CKS0 are modified when the

WDT is operating, the up-count may not be

performed correctly. Ensure that these bits

are modified only when the WDT is not

operating.

9.2.3

Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are

more difficult to write to than other registers. The procedure for writing to these registers is given

below.

Writing to WTCNT and WTCSR: These registers must be written by a word transfer

instruction. They cannot be written by a byte or longword transfer instruction. When writing to

WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in

figure 9.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the

write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.

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