HD6417618A datasheet(277/646 Pages) RENESAS

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Section 11 Ethernet Controller (EtherC)

Rev. 6.00 Jun. 12, 2007 Page 245 of 610

REJ09B0131-0600

11.3.19

IPG Register (IPGR)

IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting

and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to

section 11.4.6, Operation by IPG Setting.)

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

4 to 0

IPG4 to IPG0

H'13

R/W

Inter Packet Gap

Sets the IPG value every 4-bit time.

H'00: 20-bit time

H'01: 24-bit time

H'13: 96-bit time (Initial value)

H'1F: 144-bit time

11.3.20

Automatic PAUSE Frame Set Register (APR)

APR sets the TIME parameter value of the automatic PAUSE frame. When transmitting the

automatic PAUSE frame, the value set in this register is used as the TIME parameter of the

PAUSE frame.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

15 to 0

AP15 to AP0

All 0

R/W

Automatic PAUSE

Sets the TIME parameter value of the automatic

PAUSE frame. At this time, 1 bit means 512-bit time.

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