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HD6417618A 数据表(PDF) 285 Page - Renesas Technology Corp |
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HD6417618A 数据表(HTML) 285 Page - Renesas Technology Corp |
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285 / 646 page ![]() Section 11 Ethernet Controller (EtherC) Rev. 6.00 Jun. 12, 2007 Page 253 of 610 REJ09B0131-0600 MII Register Access Procedure: The program accesses MII registers via the PHY interface register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figure 11.9 shows the MII register access timing. The timing will differ depending on the PHY type. MDC (1) (1) (2) (3) MDO (2) (3) Write to PHY interface register 1-bit data write timing relationship MMD = 1 MDO = write data MDC = 0 MMD = 1 MDO = write data MDC = 1 Write to PHY interface register MMD = 1 MDO = write data MDC = 0 Write to PHY interface register Figure 11.6 (1) 1-Bit Data Write Flowchart |
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