R5F3640DDFB datasheet(77/398 Pages) RENESAS

77 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 56 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

Figure 8.2

Examples of Address Bus and

CSi Signal Output in 1-Mbyte Mode

Example 1

To access the external area indicated by CSj in the next cycle after

accessing the external area indicated by CSi

The address bus and chip select signal both change state between these

two cycles.

NOTE :

1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip

select bus cycle may be extended more than two cycles depending on a combination of these examples.

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the external

area indicated by CSj

Address

Data

CSj

Data

Example 2

To access the internal ROM or internal RAM in the next cycle after

accessing the external area indicated by CSi

The chip select signal changes state but the address bus does not change

state

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the internal

ROM or internal RAM

Address

Data

Example 3

To access the external area indicated by CSi in the next cycle after

accessing the external area indicated by the same CSi

The address bus changes state but the chip select signal does not change

state

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the same

external area

Address

Data

Example 4

Not to access any area (nor instruction prefetch generated) in the next cycle after

accessing the external area indicated by CSi

Neither the address bus nor the chip select signal changes state between these

two cycles

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

No access

Address

Data

Address

Shown above is the case where separate bus is selected and the area is accessed for read without wait states.

i = 0 to 3, j = 0 to 3 (not including i, however)

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