R5F3640DDFB datasheet(17/398 Pages) RENESAS

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12.2.2

Overflow Interrupt ..................................................................................... 100

12.2.4

INT Instruction Interrupt............................................................................ 100

12.3

Hardware Interrupts......................................................................................... 101

12.3.1

Special Interrupts...................................................................................... 101

12.3.2

Peripheral Function Interrupts .................................................................. 101

12.4

Interrupts and Interrupt Vector......................................................................... 102

12.4.1

Fixed Vector Tables .................................................................................. 102

12.4.2

Relocatable Vector Tables ........................................................................ 103

12.5

Interrupt Control .............................................................................................. 105

12.5.1

I Flag......................................................................................................... 107

12.5.2

IR Bit......................................................................................................... 107

12.5.3

Bits ILVL2 to ILVL0 and IPL ...................................................................... 107

12.5.4

Interrupt Sequence ................................................................................... 108

12.5.5

Interrupt Response Time .......................................................................... 109

12.5.6

Variation of IPL when Interrupt Request IS Accepted .............................. 109

12.5.7

Saving Registers ...................................................................................... 110

12.5.8

Returning from an Interrupt Routine ..........................................................111

12.5.9

Interrupt Priority .........................................................................................111

12.5.10 Interrupt Priority Level Select Circuit .........................................................111

12.6

INT Interrupt .................................................................................................... 113

12.7

NMI Interrupt ................................................................................................... 115

12.8

Key Input Interrupt........................................................................................... 115

12.9

Address Match Interrupt .................................................................................. 116

13. Watchdog Timer ................................................................................... 118

13.1

Count Source Protection Mode Disabled ........................................................ 121

13.2

Count Source Protection Mode Enabled ......................................................... 122

14. DMAC................................................................................................... 123

14.1

Transfer Cycles ............................................................................................... 129

14.1.1

Effect of Source and Destination Addresses ............................................ 129

14.1.2

Effect of BYTE Pin Level .......................................................................... 129

14.1.3

Effect of Software Wait ............................................................................. 129

14.1.4

Effect of

RDY Signal................................................................................. 129

14.2

DMA Transfer Cycles ...................................................................................... 131

14.3

DMA Enabled .................................................................................................. 132

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