R5F3640DDFB datasheet(97/398 Pages) RENESAS

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REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 76 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

10. Clock Generation Circuit

Figure 10.2

CM0 Register

b7 b6 b5 b4

System Clock Control Register 0 (1)

Symbol

CM0

Address

0006h

Bit Symbol

Bit Name

CM00

After Reset

01001000b

NOTES :

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. The CM03 bit is set to 1 (high) while the CM04 bit is set to 0 (I/O port) or when entering stop mode.

3. This bit is provided to stop the main clock when the low power consumption mode or 125 kHz on-chip oscillator

low power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock

stops or not. To stop the main clock, set bits as follows:

(a) Set the CM07 bit to 1 (sub clock selected) with the sub-clock stably oscillates, or set the CM21 bit in

the CM2 register to 1 (125 kHz on-chip oscillator selected).

(b) Set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation detection function

disabled).

4. During external clock input, set the CM05 bit to 0 (oscillate).

5. When the CM05 bit is set to 1, the XOUT pin is held “H”. Because the internal feedback resistor remains

connected, the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.

6. After setting the CM04 bit to 1 (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably

before switching the CM07 bit from 0 to 1 (sub clock).

7. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

8. The fC32 and fOCO-S clock do not stop.

9. To use a sub-clock, set this bit to 1. Also make sure ports P8_6 and P8_7 are directed for input, with no pull-

ups.

10. When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged

even if writing to bits CM02, CM05, and CM07.

11. When setting the PM21 bit to 1, set the CM07 bit to 0 (main clock) before setting the PM21 bit to 1.

12. To use the main clock as the clock source for the CPU clock, set bits as follows.

(a) Set the CM05 bit to 0 (oscillate).

(b) Wait the main clock oscillation stabilizes.

13. When the CM07 bit is set to 1 (sub clock) and the CM05 bit is set to 1 (main clock stops), the

CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capacity high).

14. To return from 125 kHz on-chip oscillator mode to high-speed or middle-speed mode, set bits CM06 and

CM15 to 1.

Function

b1 b0

0 : I/O port P5_7

1 : Output fC

0 : Output f8

1 : Output f32

Clock output function select bit

(valid only in single-chip

mode)

CM01

CM02

WAIT mode peripheral

function clock stop bit (10)

0 : Peripheral function clock f1 does not

stop in wait mode

1 : Peripheral function clock f1 stops in

wait mode (8)

CM03

XCIN-XCOUT drive capacity select

bit (2)

0 : Low

1 : High

CM04

Port XC select bit (2)

0 : I/O ports P8_6, P8_7

1 : XCIN-XCOUT oscillation function (9)

CM05

Main clock stop bit

(3, 4, 10, 12, 13)

0 : On

1 : Off (5)

CM06

Main clock division

select bit 0 (7, 13, 14)

System clock select bit

(6, 10, 11, 12)

0 : CM16 and CM17 enabled

1 : Division-by-8 mode

CM07

0 : Main clock, PLL clock, or 125 kHz on-

chip oscillator clock

1 : Sub clock

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