H8SSLASH2240 datasheet(602/818 Pages) RENESAS

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Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 560 of 772

REJ09B0355-0300

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See

table 18.3 for the method of selecting on-chip supporting modules.

Bits 15 to 0

MSTP15 to MSTP0

Description

Module stop mode cleared

Module stop mode set

18.3

Medium-Speed Mode

When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-

speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the

operating clock (

φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters

other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other

than the bus masters always operate on the high-speed clock (

φ).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if

φ/4 is selected as the operating clock, on-chip

memory is accessed in 4 states, and internal I/O registers in 8 states.

Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is

made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made

to software standby mode. When software standby mode is cleared by an external interrupt,

medium-speed mode is restored.

When the

RES pin is driven low, a transition is made to the reset state, and medium-speed mode is

cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

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