H8SSLASH2240 datasheet(604/818 Pages) RENESAS

604 / 818 page

Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 562 of 772

REJ09B0355-0300

18.5

Module Stop Mode

18.5.1

Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

Table 18.3 shows MSTP bits and the corresponding on-chip supporting modules.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating again at the end of the bus cycle. In module stop mode, the internal states of

modules other than the SCI and A/D are retained.

After reset clearance, all modules other than DTC are in module stop mode.

When an on-chip supporting module is in module stop mode, read/write access to its registers is

disabled.

If a transition is made to sleep mode when all modules are stopped (MSTPCR = H'FFFF) or

modules other than the 8-bit timers are stopped (MSTPCR = H'EFFF), operation of the bus

controller and I/O ports is also halted, enabling current dissipation to be further reduced.

H8S/2240 数据表(PDF) 604 Page - Renesas Technology Corp