H8SSLASH2240 datasheet(605/818 Pages) RENESAS

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Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 563 of 772

REJ09B0355-0300

Table 18.3

MSTP Bits and Corresponding On-Chip Supporting Modules

Bit

Module

MSTPCRH

MSTP15

—

MSTP14

Data transfer controller (DTC)

MSTP13

16-bit timer pulse unit (TPU)

MSTP12

8-bit timer

MSTP11

—

MSTP10

—

MSTP9

A/D converter

MSTP8

—

MSTPCRL

MSTP7

Serial communication interface (SCI) channel 2

MSTP6

Serial communication interface (SCI) channel 1

MSTP5

Serial communication interface (SCI) channel 0

MSTP4

—

MSTP3

—

MSTP2

—

MSTP1

—

MSTP0

—

Note:

Bits 15, 11, 10, 8, and 4 to 0 can be read or written to, but do not affect operation.

18.5.2

Usage Notes

DTC Module Stop Mode: Depending on the operating status of the DTC, the MSTP14 bit may

not be set to 1. Setting of the DTC module stop mode should be carried out only when the DTC is

not activated.

For details, refer to section 7, Data Transfer Controller.

On-Chip Supporting Module Interrupts: Relevant interrupt operations cannot be performed in

module stop mode. Consequently, if module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

Writing to MSTPCR: MSTPCR should only be written to by the CPU.

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