H8SSLASH2240 datasheet(603/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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603 / 818 page

Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 561 of 772

REJ09B0355-0300

Figure 18.1 shows the timing for transition to and clearance of medium-speed mode.

Bus master clock

φ,

supporting module

clock

Internal address

bus

Internal write signal

Medium-speed mode

SCKCR

Figure 18.1 Medium-Speed Mode Transition and Clearance Timing

18.4

Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters

sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers

are retained. Other supporting modules do not stop.

Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program

execution state via the exception handling state. Sleep mode is not cleared if interrupts are

disabled, or if interrupts other than NMI are masked by the CPU.

When the

STBY pin is driven low, a transition is made to hardware standby mode.

H8S/2240 数据表(PDF) 603 Page - Renesas Technology Corp