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H8S/2240 数据表(PDF) 194 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 194 Page - Renesas Technology Corp |
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194 / 818 page  Section 6 Bus Controller Rev.3.00 Mar. 26, 2007 Page 152 of 772 REJ09B0355-0300 6.4.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 6.6 shows the access timing for the on-chip peripheral modules. Figure 6.7 shows the pin states. T1 T2 φ Internal address bus Bus cycle Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read access Write access Figure 6.6 On-Chip Peripheral Module Access Cycle T1 T2 Bus cycle Unchanged Address bus AS RD HWR, LWR Data bus φ High High High High-impedance state Figure 6.7 Pin States during On-Chip Peripheral Module Access |
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