H8SSLASH2240 datasheet(195/818 Pages) RENESAS

195 / 818 page

Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 153 of 772

REJ09B0355-0300

6.4.3

External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 6.5.4, Basic Timing.

6.5

Basic Bus Interface

6.5.1

Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on.

The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table

6.3).

6.5.2

Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external space, controls whether the

upper data bus (D

15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications

for the area being accessed (8-bit access space or 16-bit access space) and the data size.

8-Bit Access Space

Figure 6.8 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,

the upper data bus (D

15 to D8) is always used for accesses. The amount of data that can be accessed

at one time is one byte: a word transfer instruction is performed as two byte accesses, and a

longword transfer instruction, as four byte accesses.

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