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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2240 数据表(PDF) 196 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 196 Page - Renesas Technology Corp |
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196 / 818 page  Section 6 Bus Controller Rev.3.00 Mar. 26, 2007 Page 154 of 772 REJ09B0355-0300 D15 D8 D7 D0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D 15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. D15 D8 D7 D0 Upper data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size • Even address Byte size • Odd address Lower data bus Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) |
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