H8SXSLASH1663 datasheet(582/1158 Pages) RENESAS

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Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.1.00 Jun. 07, 2006 Page 530 of 1102

REJ09B0294-0100

10.3.5

Timer Status Register (TSR)

TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.

Bit

Bit Name

Initial Value

R/W

TCFD



TCFU

R/(W)*

TCFV

R/(W)*

TGFD

R/(W)*

TGFC

R/(W)*

TGFB

R/(W)*

TGFA

R/(W)*

Note:

* Only 0 can be written to bits 5 to 0, to clear flags.

Bit

Bit Name

Initial

value

R/W

Description

TCFD

Count Direction Flag

Status flag that shows the direction in which TCNT counts

in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 7 is reserved. It is always read as

1 and cannot be modified.

0: TCNT counts down

1: TCNT counts up



Reserved

This is a read-only bit and cannot be modified.

TCFU

R/(W)* Underflow Flag

Status flag that indicates that a TCNT underflow has

occurred when channels 1, 2, 4, and 5 are set to phase

counting mode.

In channels 0 and 3, bit 5 is reserved. It is always read as

0 and cannot be modified.

[Setting condition]

When the TCNT value underflows (changes from H'0000

to H'FFFF)

[Clearing condition]

When a 0 is written to TCFU after reading TCFU = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

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