H8SXSLASH1663 datasheet(675/1158 Pages) RENESAS

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Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 623 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

OS1

OS0

R/W

Output Select 1 and 0*

These bits select a method of TMO pin output when

compare match A of TCORA and TCNT occurs.

00: No change when compare match A occurs

01: 0 is output when compare match A occurs

10: 1 is output when compare match A occurs

11: Output is inverted when compare match A occurs

(toggle output)

Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.

2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first

compare match occurs after a reset.

3. Available only in unit 0 and unit 1.

12.4

Operation

12.4.1

Pulse Output

Figure 12.5 shows an example of the 8-bit timer being used to generate a pulse output with a

desired duty cycle. The control bits are set as follows:

1. Clear the bit CCLR1 in TCR to 0 and set the bit CCLR0 in TCR to 1 so that TCNT is cleared

at a TCORA compare match.

2. Set the bits OS3 to OS0 in TCSR to B'0110, causing the output to change to 1 at a TCORA

compare match and to 0 at a TCORB compare match.

With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a

pulse width determined by TCORB. No software intervention is required. The timer output is 0

until the first compare match occurs after a reset.

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