H8SXSLASH1663 datasheet(674/1158 Pages) RENESAS

674 / 1158 page

Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 622 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CMFA

R/(W)*

Compare Match Flag A

[Setting condition]

• When TCNT matches TCORA

[Clearing conditions]

• When writing 0 after reading CMFA = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When the DTC is activated by a CMIA interrupt while

the DISEL bit in MRB of the DTC is 0

OVF

R/(W)*

Timer Overflow Flag

[Setting condition]

When TCNT overflows from H'FF to H'00

[Clearing condition]

Cleared by reading OVF when OVF = 1, then writing 0 to

OVF

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)



Reserved

This bit is always read as 1 and cannot be modified.

OS3

OS2

R/W

Output Select 3 and 2*

These bits select a method of TMO pin output when

compare match B of TCORB and TCNT occurs.

00: No change when compare match B occurs

01: 0 is output when compare match B occurs

10: 1 is output when compare match B occurs

11: Output is inverted when compare match B occurs

(toggle output)

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