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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 671 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 671 Page - Renesas Technology Corp |
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671 / 1158 page  Section 12 8-Bit Timers (TMR) Rev.1.00 Jun. 07, 2006 Page 619 of 1102 REJ09B0294-0100 12.3.6 Timer Control/Status Register (TCSR) TCSR displays status flags, and controls compare match output. • TCSR_0 • TCSR_1 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 1 R 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. • TCSR_0 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* 1 Compare Match Flag B [Setting condition] • When TCNT matches TCORB [Clearing conditions] • When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) • When the DTC is activated by a CMIB interrupt while the DISEL bit in MRB of the DTC is 0 *3 |
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