H8SXSLASH1663 datasheet(673/1158 Pages) RENESAS

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Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 621 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

OS1

OS0

R/W

Output Select 1 and 0*

These bits select a method of TMO pin output when

compare match A of TCORA and TCNT occurs.

00: No change when compare match A occurs

01: 0 is output when compare match A occurs

10: 1 is output when compare match A occurs

11: Output is inverted when compare match A occurs

(toggle output)

Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.

2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first

compare match occurs after a reset.

3. Available in unit 0 and unit 1 only.

• TCSR_1

Bit

Bit Name

Initial

Value

R/W

Description

CMFB

R/(W)*

Compare Match Flag B

[Setting condition]

• When TCNT matches TCORB

[Clearing conditions]

• When writing 0 after reading CMFB = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When the DTC is activated by a CMIB interrupt while

the DISEL bit in MRB of the DTC is 0*

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