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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 670 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 670 Page - Renesas Technology Corp |
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670 / 1158 page  Section 12 8-Bit Timers (TMR) Rev.1.00 Jun. 07, 2006 Page 618 of 1102 REJ09B0294-0100 Table 12.3 Clock Input to TCNT and Count Condition (Units 2 and 3) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description TMR_4 0 0 0 Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0 Counts at TCNT_1 overflow signal*. TMR_5 0 0 0 Clock input prohibited 0 0 1 0 0 Uses internal clock. Counts at rising edge of P φ/8. 0 1 Uses internal clock. Counts at rising edge of P φ/2. 1 0 Uses internal clock. Counts at falling edge of P φ/8. 1 1 Uses internal clock. Counts at falling edge of P φ/2. 0 1 0 0 0 Uses internal clock. Counts at rising edge of P φ/64. 0 1 Uses internal clock. Counts at rising edge of P φ/32. 1 0 Uses internal clock. Counts at falling edge of P φ/64. 1 1 Uses internal clock. Counts at falling edge of P φ/32. 0 1 1 0 0 Uses internal clock. Counts at rising edge of P φ/8192. 0 1 Uses internal clock. Counts at rising edge of P φ/1024. 1 0 Uses internal clock. Counts at rising edge of P φ. 1 1 Uses internal clock. Counts at falling edge of P φ/1024. 1 0 0 Counts at TCNT_0 compare match A*. All 1 0 1 Setting prohibited 1 1 0 Setting prohibited 1 1 1 Setting prohibited Note: * If the clock input of channel 4 is the TCNT_1 overflow signal and that of channel 5 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. |
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