H8SXSLASH1663 datasheet(692/1158 Pages) RENESAS

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Section 13 32K Timer (TM32K)

Rev.1.00 Jun. 07, 2006 Page 640 of 1102

REJ09B0294-0100

13.4

Interrupt Source

Overflows of the 32K timer generate a 32K timer interrupt (32KOVI) that lasts for three clocks of

32 kHz. Since 32KOVI is internally connected to IRQ15, the IRQ15F bit is set to 1 when an

interrupt is generated. For the IRQ15 setting, select an interrupt request generated at the falling

edge with ISCR.

Table 13.1

TM32K Interrupt Source

Name

Interrupt Source

Interrupt Flag

DTC Activation

32KOVI

TCNT32K overflow

IRQ15F

Impossible

13.5

Usage Notes

13.5.1

Changing Values of Bits CKS1 and CKS0

If bits CKS1 and CKS0 in TCR32K are written to while the TM32K is operating, errors could

occur in the incrementation. The TM32K must be stopped (the TME bit is set to 0) before the

values of bits CKS1 and CKS0 are changed.

13.5.2

Usage Notes on 32K Timer

• The 32K timer does not operate when the OSC32STP bit is set to 1. Always set the

OSC32STP bit to 0 when starting the 32K timer.

• When the OSC32STP bit has been changed from 1 to 0, allow enough time to ensure settling

of the oscillation by the 32-kHz oscillator.

13.5.3

Note on Reading Timer Counter

A counter read value is undefined during one clock of 32 kHz immediately after returning from

software standby. Wait one clock of 32 kHz when reading the timer counter.

13.5.4

Note on Register Initialization

TCR32K and TCNT32K of the 32K timer are initialized in hardware standby mode or in the pin

reset state. These registers are not initialized by a reset caused by a watchdog timer overflow.

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