H8SXSLASH1663 datasheet(695/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 14 Watchdog Timer (WDT)

Rev.1.00 Jun. 07, 2006 Page 643 of 1102

REJ09B0294-0100

14.3

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and

RSTCSR have to be written to in a method different from normal registers. For details, see section

14.6.1, Notes on Register Access.

• Timer counter (TCNT)

• Timer control/status register (TCSR)

• Reset control/status register (RSTCSR)

14.3.1

Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in

TCSR is cleared to 0.

Bit

Bit Name

Initial Value

R/W

14.3.2

Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode.

Bit

Bit Name

Initial Value

R/W

Note:

* Only 0 can be written to this bit, to clear the flag.

OVF

R/(W)*

WT/

R/W

TME

R/W



CKS2

R/W

CKS1

R/W

CKS0

R/W

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