H8SXSLASH1663 datasheet(717/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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717 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 665 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

BCP1

BCP0

R/W

Base clock Pulse 1, 0

These bits select the number of base clock cycles in a 1-

bit data transfer time in smart card interface mode.

00: 32 clock cycles (S = 32)

01: 64 clock cycles (S = 64)

10: 372 clock cycles (S = 372)

11: 256 clock cycles (S = 256)

For details, see section 15.7.4, Receive Data Sampling

Timing and Reception Margin. S is described in section

15.3.9, Bit Rate Register (BRR).

CKS1

CKS0

R/W

Clock Select 1, 0

These bits select the clock source for the baud rate

generator.

00: P

φ clock (n = 0)

01: P

φ/4 clock (n = 1)

10: P

φ/16 clock (n = 2)

11: P

φ/64 clock (n = 3)

For the relation between the settings of these bits and the

baud rate, see section 15.3.9, Bit Rate Register (BRR). n

is the decimal display of the value of n in BRR (see

section 15.3.9, Bit Rate Register (BRR)).

Note:

etu (Elementary Time Unit): 1-bit transfer time

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