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H8SX/1663 数据表(PDF) 885 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 885 Page - Renesas Technology Corp

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Section 17 I
2C Bus Interface 2 (IIC2)
Rev.1.00 Jun. 07, 2006 Page 833 of 1102
REJ09B0294-0100
17.4
Operation
17.4.1
I
2C Bus Format
Figure 17.3 shows the I
2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
S
SLA
R/
W
A
DATA
A
A/
A
P
11
1
1
n
7
1
m
(a) I2C bus format
(b) I2C bus format (start condition retransmission)
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m
≥ 1)
S
SLA
R/
W
A
DATA
11
1
n1
7
1
m1
S
SLA
R/
W
A
DATA
A/
A
P
11
1
n2
7
1
m2
1
1
1
A/
A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2
≥ 1)
11
Figure 17.3 I
2C Bus Formats
SDA
SCL
S
SLA
R/
W
A
9
8
1-7
9
8
1-7
9
8
1-7
DATA
A
DATA
A
P
Figure 17.4 I
2C Bus Timing
[Legend]
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
Slave address
R/
W:
Indicates the direction of data transfer; from the slave device to the master device when
R/
W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA low.
DATA: Transferred data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.



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