H8SXSLASH1663 datasheet(886/1158 Pages) RENESAS

886 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 834 of 1102

REJ09B0294-0100

17.4.2

Master Transmit Operation

In I

2C bus format master transmit mode, the master device outputs the transmit clock and transmit

data, and the slave device return an acknowledge signal. Figures 17.5 and 17.6 show the operating

timings in master transmit mode. The transmission procedure and operations in master transmit

mode are described below.

1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT

bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting)

2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in

ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV

instruction. (The start condition is issued.) This generates the start condition.

3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows

the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0,

data is transferred from ICDRT to ICDRS. TDRE is set again.

4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1

at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that

the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR

is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop

condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level

until the transmit data is prepared or the stop condition is issued.

5. The transmit data after the second byte is written to ICDRT every time TDRE is set.

6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last

byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the

receive device while CKE in ICIER is 1. Then, issue the stop condition to clear TEND or

NACKF.

7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.

H8SX/1663 数据表(PDF) 886 Page - Renesas Technology Corp