H8SXSLASH1663 datasheet(1009/1158 Pages) RENESAS

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Section 22 Clock Pulse Generator

Rev.1.00 Jun. 07, 2006 Page 957 of 1102

REJ09B0294-0100

Section 22 Clock Pulse Generator

This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (I

φ),

peripheral module clock (P

φ), external bus clock (Bφ), 32K timer clock (SUBCK), and USB clock

(cku).

The clock pulse generator consists of a main clock oscillator, frequency divider, PLL (phase-

locked loop) circuit, subclock oscillator, waveform generation circuit, and selector. Figure 22.1 is

a block diagram of the clock pulse generator.

The frequency divider, PLL circuit, and selector can change the clock frequency. Software

changes the frequency through the setting of the system clock control register (SCKCR) and

subclock control register (SUBCKCR).

This LSI supports five clocks: a system clock provided to the CPU and bus masters, a peripheral

module clock provided to the peripheral modules, an external bus clock provided to the external

bus, a 32K timer clock, and a USB clock provided to the USB module. Frequencies of the

peripheral module clock, the external bus clock, and the system clock can be set independently,

although the peripheral module clock and the external bus clock operate with the frequency lower

than the system clock frequency.

The system clock, peripheral module clock, and external bus clock can be uniformly set to the

32.768 kHz subclock.

The USB module requires the 48-MHz clock. Set the external clock frequency and the MD_CLK

pin so that the USB clock (cku) frequency becomes 48 MHz.

Note that the MD_CLK pin setting also changes the frequencies of the peripheral module clock,

the external bus clock, and the system clock.

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