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H8SX/1663 数据表(PDF) 1011 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 1011 Page - Renesas Technology Corp |
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1011 / 1158 page ![]() Section 22 Clock Pulse Generator Rev.1.00 Jun. 07, 2006 Page 959 of 1102 REJ09B0294-0100 22.1 Register Description The clock pulse generator has the following registers. • System clock control register (SCKCR) • Subclock control register (SUBCKCR) 22.1.1 System Clock Control Register (SCKCR) SCKCR controls B φ output control and frequencies of the system, peripheral module, and external bus clocks. Bit Bit Name Initial Value R/W 15 PSTOP1 0 R/W 14 PSTOP0 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 ICK2 0 R/W 9 ICK1 1 R/W 8 ICK0 0 R/W Bit Bit Name Initial Value R/W 7 0 R/W 6 PCK2 0 R/W 5 PCK1 1 R/W 4 PCK0 0 R/W 3 0 R/W 2 BCK2 0 R/W 1 BCK1 1 R/W 0 BCK0 0 R/W Bit Bit Name Initial Value R/W Description 15 PSTOP1 0 R/W B φ Clock Output Enable Controls φ output on PA7. • Normal operation 0: φ output 1: Fixed high 14 PSTOP0 0 R/W φ Clock Output Enable Controls φ output (SDφ) on PB7. • Normal operation 0: φ output 1: Fixed high |
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