H8SXSLASH1663 datasheet(1013/1158 Pages) RENESAS

1013 / 1158 page

Section 22 Clock Pulse Generator

Rev.1.00 Jun. 07, 2006 Page 961 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Reserved

Although this bit is readable/writable, only 0 should be

written to.

BCK2

BCK1

BCK0

R/W

External Bus Clock (B

φ) Select

These bits select the frequency of the external bus

clock. The ratio to the input clock is as follows:

BCK (2:0) MD_CLK = 0

MD_CLK = 1

000:

× 4

× 2

001:

× 2

× 1

010:

× 1

× 1/2

011:

× 1/2

Setting prohibited

1XX:

Setting prohibited

The frequency of the external bus clock should be lower

than that of the system clock. Though these bits can be

set so as to make the frequency of the external bus

clock higher than that of the system clock, the clocks

will have the same frequency in reality.

Note:

X: Don't care

22.1.2

Subclock Control Register (SUBCKCR)

SUBCKCR stops the main clock oscillator, selects the operating clock of the system clock, and

selects the operating clock after a transition from software standby mode.

Bit

Bit Name

Initial Value

R/W



R/W



R/W



R/W



R/W



R/W

EXSTP

R/W

WAKE32K

R/W

CS32K

R/W

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