H8SXSLASH1663 datasheet(1028/1158 Pages) RENESAS

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Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 976 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

SLPIE

R/W

Sleep Instruction Exception Handling Enable

Selects whether the execution of a SLEEP instruction

initiates sleep instruction exception handling or a

transition to the power-down state.

0: The execution of a SLEEP instruction does not initiate

sleep instruction exception handling.

1: The execution of a SLEEP instruction initiates sleep

instruction exception handling. After execution of the

sleep instruction exception handling, this bit remains

set to 1. Writing 0 clears this bit.

6 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

[Legend]

X: Don't care

Note:

With the F-ZTAT version, the flash memory settling time must be reserved.

23.2.2

Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)

MSTPCRA and MSTPCRB set the module stop function. Setting a bit to 1 makes the

corresponding module enter the module stop state, while clearing the bit to 0 clears the module

stop state.

• MSTPCRA

Bit

Bit Name

Initial Value

R/W

ACSE

R/W

MSTPA14

R/W

MSTPA13

R/W

MSTPA12

R/W

MSTPA11

R/W

MSTPA10

R/W

MSTPA9

R/W

MSTPA8

R/W

Bit

Bit Name

Initial Value

R/W

MSTPA7

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA2

R/W

MSTPA1

R/W

MSTPA0

R/W

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