H8SXSLASH1663 datasheet(1025/1158 Pages) RENESAS

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Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 973 of 1102

REJ09B0294-0100

Main clock operation

(CK32K = 0)

Subclock operation

(CK32K = 0)

Notes: 1. NMI, IRQ0 to IRQ11, 8-bit timer interrupts, watchdog timer interrupts, and 32K timer interrupts.

Note that the 8-bit timer interrupt is valid when the MSTPCRA9 or MSTPCRA8 bit is cleared to 0

2. NMI, IRQ0 to IRQ11, and 32K timer interrupts. Note that IRQ is valid only when the corresponding bit

in SSIER is set to 1.

3. The SLPIE bit is 0.

Notes:

• From any state, a transition to hardware standby mode occurs when STBY is driven low.

• From any state except hardware syandby mode, a transition to the reset state occurs when RES is driven low.

Reset state

Program execution state

Hardware

standby mode

Software

standby mode

SSBY = 0

SSBY = 1

SSBY = 0, ACSE = 1

MSTPCR = H'F[C-F]FFFFFF

STBY pin = high

RES pin = low

STBY pin = low

RES pin = high

SLEEP instruction

SLEEP instruction*3

SLEEP instruction

Interrupt

All interrupts

SLEEP instruction

All interrupts

CK32K = 0

CK32K = 1

Transition after exception handling

[Legend]

WAKE32K = 0

and Interrupt

Sleep mode

All-module-clock-

stop mode

Program execution state

Program halted state

SSBY = 1

Software

standby mode

SSBY = 0

SSBY = 0, ACSE = 1

MSTPCR = H'F[C-F]FFFFFF

Sleep mode

All-module-clock-

stop mode

Interrupt

WAKE32K = 1

and Interrupt

Figure 23.1 Mode Transitions

23.2

The registers related to the power-down modes are shown below. For details on the system clock

control register (SCKCR), refer to section 22.1.1, System Clock Control Register (SCKCR).

• Standby control register (SBYCR)

• Module stop control register A (MSTPCRA)

• Module stop control register B (MSTPCRB)

• Module stop control register C (MSTPCRC)

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