R4F2114R datasheet(13/1038 Pages) RENESAS

13 / 1038 page

Rev. 3.00 Jul. 14, 2005 Page xiii of xlviii

5.3.3

Break Address Registers A to C (BARA to BARC)............................................... 86

5.3.4

IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 87

5.3.5

IRQ Enable Registers (IER16, IER) ....................................................................... 90

5.3.6

IRQ Status Registers (ISR16, ISR) ......................................................................... 91

5.3.7

Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up

Event Interrupt Mask Registers (WUEMR, WUEMRB)........................................ 93

5.3.8

IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register

(ISSR) ..................................................................................................................... 97

5.4

Interrupt Sources.................................................................................................................. 99

5.4.1

External Interrupt Sources ...................................................................................... 99

5.4.2

Internal Interrupt Sources ..................................................................................... 102

5.5

Interrupt Exception Handling Vector Tables ..................................................................... 102

5.6

Interrupt Control Modes and Interrupt Operation .............................................................. 109

5.6.1

Interrupt Control Mode 0 ...................................................................................... 112

5.6.2

Interrupt Control Mode 1 ...................................................................................... 114

5.6.3

Interrupt Exception Handling Sequence ............................................................... 117

5.6.4

Interrupt Response Times ..................................................................................... 119

5.6.5

DTC Activation by Interrupt................................................................................. 120

5.7

Address Breaks ..................................................................................................................122

5.7.1

Features................................................................................................................. 122

5.7.2

Block Diagram...................................................................................................... 122

5.7.3

Operation .............................................................................................................. 123

5.7.4

Usage Notes .......................................................................................................... 123

5.8

Usage Notes ....................................................................................................................... 125

5.8.1

Conflict between Interrupt Generation and Disabling .......................................... 125

5.8.2

Instructions for Disabling Interrupts ..................................................................... 126

5.8.3

Interrupts during Execution of EEPMOV Instruction........................................... 126

5.8.4

Vector Address Switching .................................................................................... 126

5.8.5

External Interrupt Pin in Software Standby Mode and Watch Mode.................... 127

5.8.6

Noise Canceller Switching.................................................................................... 127

5.8.7

IRQ Status Register (ISR)..................................................................................... 127

Section 6 Bus Controller (BSC).........................................................................129

6.1

Features.............................................................................................................................. 129

6.2

Register Descriptions ......................................................................................................... 130

6.2.1

Bus Control Register (BCR) ................................................................................. 130

6.2.2

Wait State Control Register (WSCR) ................................................................... 131

6.3

Bus Arbitration................................................................................................................... 132

6.3.1

Priority of Bus Masters ......................................................................................... 132

6.3.2

Bus Transfer Timing ............................................................................................. 132

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