R4F2114R datasheet(21/1038 Pages) RENESAS

21 / 1038 page

Rev. 3.00 Jul. 14, 2005 Page xxi of xlviii

13.7.1 16-Bit Count Mode ............................................................................................... 403

13.7.2 Compare-Match Count Mode ............................................................................... 403

13.7.3 Input Capture Operation ....................................................................................... 404

13.8

Interrupt Sources................................................................................................................ 406

13.9

Usage Notes ....................................................................................................................... 407

13.9.1 Conflict between TCNT Write and Counter Clear................................................ 407

13.9.2 Conflict between TCNT Write and Count-Up ...................................................... 408

13.9.3 Conflict between TCOR Write and Compare-Match............................................ 409

13.9.4 Conflict between Compare-Matches A and B ...................................................... 410

13.9.5 Switching of Internal Clocks and TCNT Operation.............................................. 410

13.9.6 Mode Setting with Cascaded Connection ............................................................. 412

13.9.7 Module Stop Mode Setting ................................................................................... 412

Section 14 Watchdog Timer (WDT)..................................................................413

14.1

Features.............................................................................................................................. 413

14.2

Input/Output Pins ...............................................................................................................415

14.3

Register Descriptions ......................................................................................................... 415

14.3.1 Timer Counter (TCNT)......................................................................................... 415

14.3.2 Timer Control/Status Register (TCSR)................................................................. 416

14.4

Operation ........................................................................................................................... 420

14.4.1 Watchdog Timer Mode ......................................................................................... 420

14.4.2 Interval Timer Mode ............................................................................................. 421

14.4.3

RESO Signal Output Timing ................................................................................ 422

14.5

Interrupt Sources................................................................................................................ 423

14.6

Usage Notes ....................................................................................................................... 424

14.6.1 Notes on Register Access...................................................................................... 424

14.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 425

14.6.3 Changing Values of CKS2 to CKS0 Bits.............................................................. 426

14.6.4 Changing Value of PSS Bit................................................................................... 426

14.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode................. 426

14.6.6 System Reset by

RESO Signal ............................................................................. 426

Section 15 Serial Communication Interface (SCI, IrDA)..................................427

15.1

Features.............................................................................................................................. 427

15.2

Input/Output Pins ...............................................................................................................430

15.3

Register Descriptions ......................................................................................................... 431

15.3.1 Receive Shift Register (RSR) ............................................................................... 431

15.3.2 Receive Data Register (RDR) ............................................................................... 431

15.3.3 Transmit Data Register (TDR).............................................................................. 432

15.3.4 Transmit Shift Register (TSR) .............................................................................. 432

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