H8SLASH3006 datasheet(39/796 Pages) RENESAS

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1. Overview

Rev.5.00 Sep. 12, 2007 Page 11 of 764

REJ09B0396-0500

Pin No.

Type

Symbol

FP-100B

TFP-100B FP-100A I/O

Name and Function

RFSH

Output Refresh: Indicates a refresh cycle

DRAM

interface

2 to

89, 88, 5,

91, 90,

7, 6

Output Row address strobe

RAS: Row address

strobe signal for DRAM

Output Write enable

WE: Write enable signal for

DRAM

HWR

UCAS

Output Upper column address strobe

UCAS:

Column address strobe signal for DRAM

LWR

LCAS

Output Lower column address strobe

LCAS:

Column address strobe signal for DRAM

DREQ

5, 3

7, 5

Input

DMA request 1 and 0: DMAC activation

requests

DMA

controller

(DMAC)

TEND

94, 93

96, 95

Output Transfer end 1 and 0: These signals indicate

that the DMAC has ended a data transfer.

16-bit

timer

TCLKD to

TCLKA

96 to 93

98 to95

Input

Clock input D to A: External clock inputs

TIOCA

2 to

TIOCA

99, 97, 95 1, 99, 97 Input/

output

Input capture/output compare A2 to A0:

GRA2 to GRA0 output compare or input

capture, or PWM output

TIOCB

2 to

TIOCB

100, 98,

2, 100,

Input/

output

Input capture/output compare B2 to B0:

GRB2 to GRB0 output compare or input

capture, or PWM output

8-bit timer TMO

TMO

2, 4

4, 6

Output Compare match output: Compare match

output pins

TMIO

3, 5

5, 7

Input/

output

Input capture input/compare match output:

Input capture input or compare match output

pins

TCLKD to

TCLKA

96 to 93

98 to 95 Input

Counter external clock input: These pins

input an external clock to the counters.

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