H8SLASH3006 datasheet(97/796 Pages) RENESAS

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4. Exception Handling

Rev.5.00 Sep. 12, 2007 Page 69 of 764

REJ09B0396-0500

Section 4 Exception Handling

4.1

Overview

4.1.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction.

Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are

accepted at all times in the program execution state.

Table 4.1

Exception Types and Priority

Priority

Exception Type

Start of Exception Handling

High

Reset

Starts immediately after a low-to-high transition at the RES pin

Interrupt

Interrupt requests are handled when execution of the current

instruction or handling of the current exception is completed

Low

Trap instruction

(TRAPA)

Started by execution of a trap instruction (TRAPA)

4.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.

1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.

2. The CCR interrupt mask bit is set to 1.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

Note:

For a reset exception, steps 2 and 3 above are carried out.

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