M16CSLASH26 datasheet(33/239 Pages) RENESAS

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Processor Mode

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Table 1.7.1. Software waits and bus cycles

Area

Wait bit

Bus cycle

2 BCLK cycles

Internal

ROM/RAM

1 BCLK cycle

Software wait

A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address

000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).

A software wait is inserted in the internal ROM/RAM area by setting the wait bit of processor mode register

1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is

executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". When set to

"1", a wait is applied to all memory areas (two BCLK cycles). Set this bit after referring to the recommended

operating conditions (main clock input oscilliation frequecny) of the electrical characteristics.

The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.

Table 1.7.1 shows the software wait and bus cycles.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

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