M16CSLASH26 datasheet(17/239 Pages) RENESAS

部件名	M16C/26

功能描述	16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES

PDF	239 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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17 / 239 page

Renesas Technology Corp.

CPU

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

• Bits 8 to 11: Reserved area

• Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight

processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

• Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for

details.

Figure 1.4.3. Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Flag register (FLG)

b15

M16C/26 数据表(PDF) 17 Page - Renesas Technology Corp