7733 datasheet(53/940 Pages) RENESAS

53 / 940 page

CENTRAL PROCESSING UNIT (CPU)

7733 Group User’s Manual

2–14

2.2.3 Operation of bus interface unit (BIU)

Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). When accessing external

devices, some signals which are input or output to or from the external are required. For details about

these signals, refer to chapter “12. CONNECTING EXTERNAL DEVICES.”

(1) When fetching an instruction into an instruction queue buffer

When an instruction which is next fetched resides at an even address

The BIU fetches two bytes of the instruction with waveform (a).

Note that when an external device which is connected by an 8-bit external data bus (BYTE = “H”)

is accessed, only one byte of the instruction is fetched.

When an instruction which is next fetched resides at an odd address

The BIU fetches only one byte of the instruction with waveform (a). The contents at an even

address is not fetched into an instruction queue buffer.

(2) When reading or writing data from or to memory • I/O

When accessing 16-bit data which starts from an even address, waveform (a) is applied. The 16-

bit data is accessed at a time.

When accessing 16-bit data which starts from an odd address, waveform (b) is applied. The 16-bit

data is accessed by the 8 bits. Invalid data is not fetched into a data buffer.

When accessing 8-bit data at an even address, waveform (a) is applied. Data at an odd address

is not fetched into a data buffer.

When accessing 8-bit data at an odd address, waveform (a) is applied. Data at an even address

is not fetched into a data buffer.

For instructions which are affected by the data length flag (m) or index register length flag (x), an

operation is applied as follows:

• When “m” or “x” = “0,” operation or is applied.

• When “m” or “x” = “1,” operation or is applied.

2.2 Bus interface unit

7733 数据表(PDF) 53 Page - Renesas Technology Corp